Chun Jason Xue

 Submitted Journal Papers

1. C. Xue, Q. Zhuge, Z. Shao, and E. H.-M. Sha, "Iterational Retiming with Partitioning: Loop Scheduling with Complete Memory Latency Hiding"   Submitted to ACM Transaction on Embedded Computing System (TECS). (Under Revision)



2. C. Xue, Z. Shao, Q. Zhuge, M.K. Qiu, and E. H.-M. Sha, "Register and Memory Sensitive Loop Scheduling and Partitioning"  Submitted to IEEE Transaction on Parallel and Distributed Computing (TPDS).



3. C. Xue, Z. Shao, M.K. Qiu, and E. H.-M. Sha, "Optimize Address Assignment with Array and Loop Transformation for minimizing schedule length"   Submitted to IEEE Transaction on Circuits and System. (Under Revision)

Conference Papers

1. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Scheduling with Complete Memory Latency Hiding on Multi-core architecture," Accepted in Proc. the 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS), Vol 1, pp. 375-382, July 2006.
   
   
2. M. Qiu, C. Xue, Z. Shao, and E. H.-M. Sha `` Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems," Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) , Acropolis, Nice, France, April 16-20, 2007
   
   
3. M. Liu, C. Xue, M. Qiu, and E. H.-M. Sha `` Optimizing Timing and Code Size Using Maximum Direct Loop Fusion," Accepted in Proc. The 19th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2006), San Francisco, CA, Sept. 2006.
   
   
4. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha `` Loop Striping: Maximize Parallelism for Nested Loops," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer. Korea, Aug 2006
   
   
5. M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu, and E. H.-M. Sha `` Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability," Accepted in Proc. IEEE 17th international conference on Application-specific Systems, Architectures and Processors (ASAP), Sep 2006.
   
   
6. M. Qiu, Z. Jia, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Scheduling to Minimize Cost with Data Mining and Prefetching for Heterogeneous DSP," Accepted in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), Dallas, Texas, Nov. 2006.
   
   
7. M. Qiu, C. Xue Z. Shao, M. Liu, and E. H.-M. Sha `` Efficent Algorithm of Energy Minimization for Heterogeneour Wireless Sensor Network," Accepted in Proc. 2006 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2006), Lecture Note in Computer Science (LNCS), Springer. Korea, Aug 2006
   
   
8. M. Qiu, Z. Shao, Qingfeng Zhuge, C. Xue, M. Liu, and E. H.-M. Sha `` Efficient Assignment with Guraranteed Probability for Heterogeneous Parallel DSP," Accepted in Proc. the 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS), July. 2006.
   
   
9. M. Liu, Q. Zhuge, Z. Shao, C. Xue and E. H.-M. Sha `` Loop Distribution and Fusion for Embedded DSP Applications Considering Code Size," Accepted in Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), Las Vegas, Nevada, Dec. 2005.
   
   
10. M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha `` Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems," Accepted in Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, Phoenix, Arizona, Nov. 2005.
    
    
11. C. Xue, Z. Shao, M. Liu, M.K. Qiu and E. H.-M. Sha, `` Optimizing Nested Loops with Iterational and Instructional Retiming," Accepted in Proc. 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC'2005), Lecture Note in Computer Science (LNCS), Springer. Nagasaki, Japan, 6-9 December 2005
    
    
12. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, `` Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP," Accepted in Proc. The 2005 IFIP International Conference on Embedded And Ubiquitous Computing (EUC-05), Lecture Note in Computer Science (LNCS), Springer. Nagasaki, Japan, Dec. 2005.
    
    
13. C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops," Accepted in Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), New York, New York, Sept. 2005.
    
    
14. M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, ``Multi-level Loop Fusion with Minimal Code Size," Accepted in Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), Las Vegas, Sept. 2005.
    
    
15. Y. Chen, Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems," Accepted in Proc. The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005(Best workshop paper).
    
    
16. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, `` Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software", in Proc. IEEE International Conference on Information Technology (ITCC 05), Information Assurance and Security Track , Las Vegas, NV, April 2005.
    
    
17. C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, ``Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation", in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005), Philadelphia, PA, March 2005(Winner of the Best Student paper ).
    
    
18. Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, ``High-level Synthesis for DSP Applications using Heterogeneous Functional Units", in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 2005), Shanghai, China, Jan. 2005.
    
    
19. C. Xue, Z. Shao, E. H.-M. Sha and B. Xiao, ``Optimizing Address Assignment for Scheduling Embedded DSPs," in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC 2004),, pp. 64-73, Lecture Note in Computer Science (LNCS), Springer, Aizu-Wakamatsu City, Japan, August, 2004.
    
    
20. Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu and E. H.-M. Sha, ``Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units," in 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM Proceeding, Santa Fe, Apr. 2004.
    
    
21. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao,`` Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks," In Proc. Information Assurance and Security special track in conjunction with International Conference on Information Technology: Coding and Computing (ITCC 2004), Volume I, pp. 409-413, Las Vegas, Apr. 2004.
    
    

Awards

1. Best paper award (Title: Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation) in the 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing. A total of 30 Awards are selected from a field of 1400 proceedings, and the only award in the design and implementation of Signal Processing Systems track.
   
   
2. Best paper award (Title: Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems) in the IEEE/IFIP International Workshop on Parallel and Distributed Embedded Systems in conjunction with ICPADS 2005, Fukuoka, Japan, July 2005.

Teaching and Presentation

1. Digital Signal Processing and Applications with the TMS320C6713 and the TMS3206416 DSK by TI. Topics include introduction to Code Composer Studio IDE, Architecture of the C6000 floating-point processor,Programming the TMS320C6713 DSP on the DSK, and DSP applications, with enough information and tools to fully implement a lab course using TI DSP.
   
   
2. Teach VHDL simulation and synthesis with Xilinx ISE 8.1i, in Spring 2006 CS6397.

Patent

1. "Parallel Variable Length Pattern Matching Using Hash Table", Chun Xue, Edwin Sha, Meikang Qiu, Qingfeng Zhuge.
   U. S. Patent, Serial No. 11/307,864, filed Feb 26th, 2006.
   
   
2. "Minimize Energy Consumption Using Optimal Voltage Assignment Algorithm", Meikang Qiu, Edwin H.-M. Sha, Chun Xue, and Qingfeng Zhuge. U. S. Patent, Serial No. 11/307,924, filed Feb 28th, 2006.

Professional Activity

1. Session Chair, session IIB - Parallel and Distributed Algorithms, ICPADS 2006.
   
   

Education