Nanoscale Strains in Si CMOS

µ Strained-Si CMOS characterization technology

µ Experimental procedure

   Ø Site-specific sample preparation by FIB and thickness effect on CBED

   Ø Choice of Zone Axis

   Ø CBED pattern simulation and strain calculation

µ Analysis of Strain-engineered Si CMOS

   Ø Si PMOS with SiGe in S/D

   Ø One-dimensional strain map

   Ø Si NMOS with SiN capping

   Ø STI w/wo Trench Filling

   Ø Process-induced strain

   Ø Strain relaxation in Si1-xGex/Si

 

 

Strained-Si Technology with Questions

 

 

Direct Strain Measurement Metrology

  Spatial

Resolution

 Strain

Sensitivity

 Strain

Components

 Model or

Simulation

 Sample

Prep
X-ray

Diffraction

 50μm 10-6 2 No No
Mico-

Raman

 1μm 10-4 1 Yes No
TEM

CBED

 10nm 10-4 3 Yes Yes