Nanoscale Strains in Si CMOS

µ Strained-Si CMOS characterization technology

µ Experimental procedure

   Ø Site-specific sample preparation by FIB and thickness effect on CBED

   Ø Choice of Zone Axis

   Ø CBED pattern simulation and strain calculation

µ Analysis of Strain-engineered Si CMOS

   Ø Si PMOS with SiGe in S/D

   Ø One-dimensional strain map

   Ø Si NMOS with SiN capping

   Ø STI w/wo Trench Filling

   Ø Process-induced strain

   Ø Strain relaxation in Si1-xGex/Si

 

 

Mechanical polishing

 

Sample ion-milled by FIB

 

SEM image (top-view) after FIB preparation

 

SEM image of the device (side-view)

The pretective Pt layer is deposited on top